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| ISPPAC-POWR1014/A In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller August 2007 Data Sheet DS1014 (R) Features Monitor and Control Multiple Power Supplies * Simultaneously monitors up to 10 power supplies * Provides up to 14 output control signals * Programmable digital and analog circuitry Application Block Diagram Primary Supply 3.3V Primary Supply 2.5V Primary Supply 1.8V Primary Supply Embedded PLD for Sequence Control * 24-macrocell CPLD implements both state machines and combinatorial logic functions Analog Input Monitoring * 10 independent analog monitor inputs * Two programmable threshold comparators per analog input * Hardware window comparison * 10-bit ADC for I2C monitoring (ispPACPOWR1014A only) Primary Supply POL#N Other Control/Supervisory Signals 12 Digital Outputs 2 MOSFET Drivers Enables * Four independent timers * 32s to 2 second intervals for timing sequences Voltage Monitoring Embedded Programmable Timers POL#1 10 Analog Inputs and Voltage Monitors High-Voltage FET Drivers * Power supply ramp up/down control * Programmable current and voltage output * Independently configurable for FET control or digital output CPLD 24 Macrocells 53 Inputs ADC* 4 Timers 4 Digital Inputs I2C Interface I2C Bus* CPU ISPPAC-POWR1014A *ISPPAC-POWR1014A only. 2-Wire (I2C/SMBusTM Compatible) Interface * * * * * Comparator status monitor ADC readout Direct control of inputs and outputs Power sequence control Only available with ISPPAC-POWR1014A Description Lattice's Power Manager II ISPPAC-POWR1014/A is a general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2CMOS(R) technology. The ISPPAC-POWR1014/A device provides 10 independent analog input channels to monitor up to 10 power supply test points. Each of these input channels has two independently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-compare) monitor functions. Four general-purpose digital inputs are also provided for miscellaneous control functions. The ISPPAC-POWR1014/A provides 14 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Two of these outputs (HVOUT1-HVOUT2) may be configured as high-voltage 3.3V Operation, Wide Supply Range 2.8V to 3.96V * In-system programmable through JTAG * Industrial temperature range: -40C to +85C * 48-pin TQFP package, lead-free option (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1014_01.5 Digital Monitoring Other Board Circuitry Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet MOSFET drivers. In high-voltage mode these outputs can provide up to 10V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. The ISPPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32s to 2 seconds. The CPLD is programmed using LogiBuilderTM, an easy-to-learn language integrated into the PAC-Designer(R) software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. The on-chip 10-bit A/D converter is used to monitor the VMON voltage through the I2C bus of the ispPACPOWR1014A device. The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON inputs, read back the status of each of the VMON comparator and PLD outputs, control logic signals IN2 to IN4 and control the output pins (ISPPAC-POWR1014A only). Figure 1. ISPPAC-POWR1014/A Block Diagram ADC* MEASUREMENT CONTROL LOGIC* VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 10 ANALOG INPUTS AND VOLTAGE MONITORS 4 DIGITAL INPUTS 2 FET DRIVERS HVOUT1 HVOUT2 OUTPUT ROUTING POOL CPLD 24 MACROCELLS 53 INPUTS IN1 IN2 IN3 IN4 JTAG LOGIC CLOCK OSCILLATOR TIMERS (4) I 2C INTERFACE OUT3/(SMBA*) OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 12 OPEN-DRAIN DIGITAL OUTPUTS GNDA SCL (POWR1014A on SDA (POWR1014A on *ISPPAC-POWR1014A only. VCCINP ATDI TDI TDISEL TCK TMS TDO VCCJ PLDCLK MCLK RESETb VCCD (2) VCCA GNDD (2) VCCPROG 2 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Pin Descriptions Number 44 46 47 48 25 26 27 28 32 33 34 35 36 37 7, 31 30 29 45 20 24 IN1 IN2 IN3 IN4 VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 GNDD5 GNDA VCCA VCCJ VCCPROG 5 6 Name Pin Type Digital Input Digital Input Digital Input Digital Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Ground Ground Power Power Power Power Power Open Drain Output7 Voltage Range VCCINP1 VCCINP1 VCCINP1 VCCINP 1 4 Description PLD Logic Input 1 Registered by MCLK PLD Logic Input 2 Registered by MCLK PLD Logic Input 3 Registered by MCLK PLD Logic Input 4 Registered by MCLK Voltage Monitor 1 Input Voltage Monitor 2 Input Voltage Monitor 3 Input Voltage Monitor 4 Input Voltage Monitor 5 Input Voltage Monitor 6 Input Voltage Monitor 7 Input Voltage Monitor 8 Input Voltage Monitor 9 Input Voltage Monitor 10 Input Digital Ground Analog Ground Core VCC, Main Power Supply Analog Power Supply VCC for IN[1:4] Inputs VCC for JTAG Logic Interface Pins VCC for E2 Programming when the Device is Not Powered by VCCD and VCCA Open-Drain Output 1 -0.3V to 5.87V -0.3V to 5.87V4 -0.3V to 5.87V4 -0.3V to 5.87V4 -0.3V to 5.87V4 -0.3V to 5.87V4 -0.3V to 5.87V -0.3V to 5.87V Ground Ground 2.8V to 3.96V 2.8V to 3.96V 2.25V to 5.5V 2.25V to 3.6V 3.0V to 3.6V 0V to 10V 4 -0.3V to 5.87V4 4 -0.3V to 5.87V4 41, 23 VCCD 6 VCCINP 15 HVOUT1 Current Source/Sink Open Drain Output7 12.5A to 100A Source High-voltage FET Gate Driver 1 100A to 3000A Sink 0V to 10V Open-Drain Output 2 12.5A to 100A Source High-voltage FET Gate Driver 2 100A to 3000A Sink 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 3.96V 0V to 3.96V Open-Drain Output 3, (SMBUS Alert Active Low, ISPPAC-POWR1014A only). Open-Drain Output 4 Open-Drain Output 5 Open-Drain Output 6 Open-Drain Output 7 Open-Drain Output 8 Open-Drain Output 9 Open-Drain Output 10 Open-Drain Output 11 Open-Drain Output 12 Open-Drain Output 13 Open-Drain Output 14 Device Reset (Active Low) - Internal pull-up 250kHz PLD Clock Output (Tristate), CMOS Output - Internal pull-up 14 HVOUT2 Current Source/Sink 13 12 11 10 9 8 6 5 4 3 2 1 40 42 SMBA_OUT3 Open Drain Output7 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 RESETb8 PLDCLK Open Drain Output7 Open Drain Output Open Drain Output Open Drain Output 7 7 7 7 Open Drain Output Open Drain Output7 Open Drain Output7 Open Drain Output7 Open Drain Output7 Open Drain Output7 Open Drain Output Digital I/O Digital Output 7 3 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Pin Descriptions (Cont.) Number 43 21 22 16 18 17 19 39 38 Name MCLK TDO TCK TMS TDI ATDI TDISEL SCL9 SDA9 Pin Type Digital I/O Digital Output Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input Digital I/O Voltage Range 0V to 3.96V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V Description 8MHz Clock I/O (Tristate), CMOS Drive - Internal Pull-up JTAG Test Data Out JTAG Test Clock Input JTAG Test Mode Select - Internal Pull-up JTAG Test Data In, TDISEL pin = 1 - Internal Pull-up JTAG Test Data In (Alternate), TDISEL Pin = 0 Internal Pull-up Select TDI/ATDI Input - Internal Pull-up I2C Serial Clock Input (ISPPAC-POWR1014A Only) I2C Serial Data, Bi-directional Pin, Open Drain (ISPPAC-POWR1014A Only) 1. [IN1...IN4] are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCCINP. Unused INx inputs should be tied to GNDD. 2. IN1 pin can also be controlled through JTAG interface. 3. [IN2..IN4] can also be controlled through I2C/SMBus interface (ISPPAC-POWR1014A only). 4. The VMON inputs can be biased independently from VCCA. Unused VMON inputs should be tied to GNDD. 5. GNDA and GNDD pins must be connected together on the circuit board. 6. VCCD and VCCA pins must be connected together on the circuit board. 7. Open-drain outputs require an external pull-up resistor to a supply. 8. The RESETb pin should only be used for cascading two or more ISPPAC-POWR1014/A devices. 9. These pins should be connected to GNDD (ISPPAC-POWR1014 device only). 4 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Absolute Maximum Ratings Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this specification is not implied. Symbol VCCD VCCA VCCINP VCCJ VCCPROG VIN VMON VTRI ISINKMAXTOTAL TS TA Core supply Analog supply Digital input supply (IN[1:4]) JTAG logic supply E programming supply Digital input voltage (all digital I/O pins) VMON input voltage Voltage applied to tri-stated pins Maximum sink current on any output Storage temperature Ambient temperature -65 -65 HVOUT[1:2] OUT[3:14] 2 Parameter Conditions Min. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 Max. 4.5 4.5 6 6 4 6 6 11 6 23 150 125 Units V V V V V V V V V mA o o C C Recommended Operating Conditions Symbol VCCD, VCCA VCCINP VCCJ VCCPROG VIN VMON VOUT TAPROG TA Parameter Core supply voltage at pin Digital input supply for IN[1:4] at pin JTAG logic supply voltage at pin E2 programming supply at pin Input voltage at digital input pins Input voltage at VMON pins OUT[3:14] pins Open-drain output voltage Ambient temperature during programming Ambient temperature Power applied HVOUT[1:2] pins in opendrain mode During E2 programming Conditions Min. 2.8 2.25 2.25 3.0 -0.3 -0.3 -0.3 -0.3 -40 -40 Max. 3.96 5.5 3.6 3.6 5.5 5.9 5.5 10.4 85 85 Units V V V V V V V V o C C o Analog Specifications Symbol ICC 1 Parameter Supply current Supply current Supply current Supply current Conditions Min. Typ. Max. 20 5 1 Units mA mA mA mA ICCINP ICCJ ICCPROG During programming cycle 20 1. Includes currents on VCCD and VCCA supplies. 5 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Voltage Monitors Symbol RIN CIN VMON Range VZ Sense VMON Accuracy HYST Parameter Input resistance Input capacitance Programmable trip-point range Near-ground sense threshold Absolute accuracy of any trip-point 1 Conditions Min. 55 0.075 70 Typ. 65 8 Max. 75 5.867 Units k pF V mV % % 75 0.3 1 80 0.9 Hysteresis of any trip-point (relative to setting) 1. Guaranteed by characterization across VCCA range, operating temperature, process. High Voltage FET Drivers Symbol VPP Parameter Gate driver output voltage Conditions 10V setting 8V setting 6V setting Gate driver source current (HIGH state) Min. 9.6 7.7 5.8 Typ. 10 8 6 12.5 IOUTSRC Four settings in software 25 50 100 FAST OFF mode IOUTSINK Gate driver sink current (LOW state) Controlled ramp settings 2000 3000 100 250 500 A A Max. 10.4 8.3 6.2 V Units 6 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet ADC Characteristics1 Symbol TCONVERT VIN Parameter ADC resolution Conversion time Input range full scale Time from I2C request Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 3 0 0 2 6 +/- 0.1 Conditions Min. Typ. 10 100 2.048 5.9 2 Max. Units Bits s V V mV mV % ADC Step Size LSB Eattenuator Error due to attenuator 1. ISPPAC-POWR1014A only. 2. Maximum voltage is limited by VMONX pin (theoretical maximum is 6.144V). ADC Error Budget Across Entire Operating Temperature Range1 Symbol TADC Error Parameter Total Measurement Error at Any Voltage2 Conditions Measurement Range 600 mV - 2.048V, Attenuator =1 Min. -8 Typ. +/-4 Max. 8 Units mV 1. ISPPAC-POWR1014A only. 2. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC. Power-On Reset Symbol TGOOD VTL VTH VT TPOR CL Parameter Power-on reset to valid VMON comparator output Threshold below which RESETb is LOW1 Threshold above which RESETb is HIGH Threshold above which RESETb is valid1 Minimum duration dropout required to trigger RESETb Capacitive load on RESETb for master/slave operation 1 Conditions Min. Typ. Max. 500 2.3 Units s V V V 2.7 0.8 1 5 200 s pF 1. Corresponds to VCCA and VCCD supply voltages. 7 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet AC/Transient Characteristics Over Recommended Operating Conditions Symbol Voltage Monitors tPD16 tPD64 Oscillators fCLK fCLKEXT fPLDCLK Timers Timeout Range Resolution Accuracy Range of programmable timers (128 steps) Spacing between available adjacent timer intervals Timer accuracy fCLK = 8MHz -6.67 fCLK = 8MHz 0.032 1966 13 -12.5 ms % % Internal master clock frequency (MCLK) Externally applied master clock (MCLK) PLDCLK output frequency fCLK = 8MHz 7.6 7.2 250 8 8.4 8.8 MHz MHz kHz Propagation delay input to output glitch filter OFF Propagation delay input to output glitch filter ON 16 64 s s Parameter Conditions Min. Typ. Max. Units 8 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Digital Specifications Over Recommended Operating Conditions Symbol IIL,IIH IOH-HVOUT Parameter Input leakage, no pull-up/pull-down Output leakage current Input pull-up current (TMS, TDI, TDISEL, ATDI, MCLK, PLDCLK, RESETb) TDI, TMS, ATDI, TDISEL, 3.3V supply VIL Voltage input, logic low1 TDI, TMS, ATDI, TDISEL, 2.5V supply SCL, SDA IN[1:4] TDI, TMS, ATDI, TDISEL, 3.3V supply VIH Voltage input, logic high1 TDI, TMS, ATDI, TDISEL, 2.5V supply SCL, SDA IN[1:4] HVOUT[1:2] (open drain mode), VOL VOH OUT[3:14] TDO,MCLK,PLDCLK TDO, MCLK, PLDCLK ISINKTOTAL2 All digital outputs ISINK = 10mA ISINK = 20mA ISINK = 4mA ISRC = 4mA 2.0 1.7 70% VCCD 70% VCCINP VCCD VCCINP 0.8 0.8 0.4 VCCD - 0.4 67 V mA V V HVOUT[1:2] in open drain mode and pulled up to 10V 35 Conditions Min. Typ. Max. +/-10 60 Units A A IPU 70 0.8 0.7 30% VCCD 30% VCCINP A V 1. IN[1:4] referenced to VCCINP; TDO, TDI, TMS, ATDI, TDISEL referenced to VCCJ; SCL, SDA referenced to VCCD. 2. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded. 9 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet I2C Port Characteristics1 100KHz Symbol FI2C TSU;STA THD;STA TSU;DAT TSU;STO THD;DAT TLOW THIGH TF TR TTIMEOUT TPOR TBUF I C clock/data rate After start After start Data setup Stop setup Data hold; SCL= Vih_min = 2.1V Clock low period Clock high period Fall time; 2.25V to 0.65V Rise time; 0.65V to 2.25V Detect clock low timeout Device must be operational after power-on reset Bus free time between stop and start condition 25 500 4.7 4.7 4 250 4 0.3 4.7 4 300 1000 35 25 500 1.3 3.45 10 2 400KHz Min. 0.6 0.6 100 0.6 0.3 1.3 0.6 300 300 35 0.9 10 Max. 400 2 Definition Min. Max. 100 2 Units KHz us us ns us us us us ns ns ms ms us 1. Applies to ISPPAC-POWR1014A only. 2. If FI2C is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this case, waiting for the TCONVERT minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for readout. When FI2C is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit. 10 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Timing for JTAG Operations Symbol tISPEN tISPDIS tHVDIS tHVDIS tCEN tCDIS tSU1 tH tCKH tCKL fMAX tCO tPWV tPWP Parameter Program enable delay time Program disable delay time High voltage discharge time, program High voltage discharge time, erase Falling edge of TCK to TDO active Falling edge of TCK to TDO disable Setup time Hold time TCK clock pulse width, high TCK clock pulse width, low Maximum TCK clock frequency Falling edge of TCK to valid output Verify pulse width Programming pulse width Conditions Min. 10 30 30 200 -- -- 5 10 20 20 -- -- 30 20 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- 10 10 -- -- -- -- 25 10 -- -- Units s s s s ns ns ns ns ns ns MHz ns s ms Figure 2. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL tSU1 VIH tH tCKH tSU1 tGKL tH tSU1 Clock to Shift-IR state and shift in the Discharge Instruction, then clock to the Run-Test/Idle state tH tCKH tSU1 tH tCKH tSU1 tGKL tH tCKH tSU1 tH tCKH TCK VIL tSU2 Specified by the Data Sheet State Update-IR Run-Test/Idle (Erase) Select-DR Scan Run-Test/Idle (Discharge) Figure 3. Programming Timing Diagram VIH TMS VIL tSU1 VIH tH tCKH tSU1 tCKL tH tPWP tSU1 tH tCKH Clock to Shift-IR state and shift in the next Instruction, which will stop the discharge process tSU1 tH tCKH tSU1 tCKL tH tCKH TCK VIL State Update-IR Run-Test/Idle (Program) Select-DR Scan Update-IR 11 Lattice Semiconductor Figure 4. Verify Timing Diagram VIH ISPPAC-POWR1014/A Data Sheet TMS VIL tSU1 VIH tH tCKH tSU1 tCKL tH tPWV tSU1 tH tCKH Clock to Shift-IR state and shift in the next Instruction tSU1 tH tCKH tSU1 tCKL tH tCKH TCK VIL State Update-IR Run-Test/Idle (Program) Select-DR Scan Update-IR Figure 5. Discharge Timing Diagram VIH tHVDIS (Actual) Clock to Shift-IR state and shift in the Verify Instruction, then clock to the Run-Test/Idle state TMS VIL tSU1 VIH tH tCKH tSU1 tCKL tH tPWP tSU1 tH tCKH tSU1 tH tCKH tSU1 tCKL tH tCKH tSU1 tPWV Actual tH tCKH TCK VIL tPWV Specified by the Data Sheet State Update-IR Run-Test/Idle (Erase or Program) Select-DR Scan Run-Test/Idle (Verify) Theory of Operation Analog Monitor Inputs The ISPPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in Figure 6. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 372 programmable trip points over the range of 0.672V to 5.867V. Additionally, a 75mV `zero-detect' threshold is selectable which allows the voltage monitors to determine if a monitored signal has dropped to ground level. This feature is especially useful for determining if a power supply's output has decayed to a substantially inactive condition after it has been switched off. 12 Lattice Semiconductor Figure 6. ISPPAC-POWR1014/A Voltage Monitors ISPPAC-POWR1014/A ISPPAC-POWR1014/A Data Sheet To ADC (POWR1014A only) Comp A VMONx Trip Point A + Comp A/Window Select VMONxA Logic Signal MUX - Glitch Filter PLD Array Comp B + Trip Point B - Glitch Filter VMONxB Logic Signal Analog Input Window Control Filtering VMONx Status I2C Interface Unit (POWR1014A only) Figure 6 shows the functional block diagram of one of the 10 voltage monitor inputs - `x' (where x = 1...10). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. The voltage input is monitored by two individually programmable trip-point comparators, shown as CompA and CompB. Table 1 shows all trip points and the range to which any comparator's threshold can be set. Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than its programmed trip point setting, otherwise it outputs a LOW signal. A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 3 lists the typical hysteresis versus voltage monitor trip-point. AGOOD Logic Signal All the VMON comparators auto-calibrate immediately after a power-on reset event. During this time, the digital glitch filters are also initialized. This process completion is signalled by an internally generated logic signal: AGOOD. All logic using the VMON comparator logic signals must wait for the AGOOD signal to become active. Programmable Over-Voltage and Under-Voltage Thresholds Figure 7 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the comparator outputs change state at different thresholds depending on the direction of excursion of the monitored power supply. 13 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Figure 7. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator Output, (b) Corresponding to Upper and Lower Trip Points Monitored Power Supply Votlage UTP LTP (a) (b) Comparator Logic Output During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP should be used. To monitor under-voltage fault conditions, the LTP should be used. Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in software depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. 14 Lattice Semiconductor Table 1. Trip Point Table Used For Over-Voltage Detection Coarse Range Setting Fine Range Setting 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Low-V Sense ISPPAC-POWR1014/A Data Sheet 1 0.806 0.802 0.797 0.793 0.789 0.785 0.781 0.776 0.772 0.768 0.764 0.760 0.755 0.751 0.747 0.743 0.739 0.734 0.730 0.726 0.722 0.718 0.713 0.709 0.705 0.701 0.697 0.692 0.688 0.684 0.680 2 0.960 0.955 0.950 0.945 0.940 0.935 0.930 0.925 0.920 0.915 0.910 0.905 0.900 0.895 0.890 0.885 0.880 0.875 0.870 0.865 0.860 0.855 0.850 0.845 0.840 0.835 0.830 0.825 0.820 0.815 0.810 3 1.143 1.137 1.131 1.125 1.119 1.113 1.107 1.101 1.095 1.089 1.083 1.077 1.071 1.065 1.059 1.053 1.047 1.041 1.035 1.029 1.024 1.018 1.012 1.006 1.000 0.994 0.988 0.982 0.976 0.970 0.964 4 1.360 1.353 1.346 1.338 1.331 1.324 1.317 1.310 1.303 1.296 1.289 1.282 1.275 1.268 1.261 1.254 1.246 1.239 1.232 1.225 1.218 1.211 1.204 1.197 1.190 1.183 1.176 1.169 1.161 1.154 1.147 5 1.612 1.603 1.595 1.586 1.578 1.570 1.561 1.553 1.544 1.536 1.528 1.519 1.511 1.502 1.494 1.486 1.477 1.469 1.460 1.452 1.444 1.435 1.427 1.418 1.410 1.402 1.393 1.385 1.377 1.368 -- 6 1.923 1.913 1.903 1.893 1.883 1.873 1.863 1.853 1.843 1.833 1.823 1.813 1.803 1.793 1.783 1.773 1.763 1.753 1.743 1.733 1.723 1.713 1.703 1.693 1.683 1.673 1.663 1.653 1.643 1.633 1.623 7 2.290 2.278 2.266 2.254 2.242 2.230 2.219 2.207 2.195 2.183 2.171 2.159 2.147 2.135 2.123 2.111 2.099 2.087 2.075 2.063 2.052 2.040 2.028 2.016 2.004 1.992 1.980 1.968 1.956 1.944 1.932 8 2.719 2.705 2.691 2.677 2.663 2.649 2.634 2.620 2.606 2.592 2.578 2.564 2.550 2.535 2.521 2.507 2.493 2.479 2.465 2.450 2.436 2.422 2.408 2.394 2.380 2.365 2.351 2.337 2.323 2.309 2.295 9 3.223 3.206 3.190 3.173 3.156 3.139 3.122 3.106 3.089 3.072 3.055 3.038 3.022 3.005 2.988 2.971 2.954 2.938 2.921 2.904 2.887 2.871 2.854 2.837 2.820 2.803 2.787 2.770 2.753 2.736 -- 10 3.839 3.819 3.799 3.779 3.759 3.739 3.719 3.699 3.679 3.659 3.639 3.619 3.599 3.579 3.559 3.539 3.519 3.499 3.479 3.459 3.439 3.419 3.399 3.379 3.359 3.339 3.319 3.299 3.279 3.259 3.239 11 4.926 4.900 4.875 4.849 4.823 4.798 4.772 4.746 4.721 4.695 4.669 4.644 4.618 4.592 4.567 4.541 4.515 4.490 4.464 4.438 4.413 4.387 4.361 4.336 4.310 4.284 4.259 4.233 4.207 4.182 4.156 12 5.867 5.836 5.806 5.775 5.745 5.714 5.683 5.653 5.622 5.592 5.561 5.531 5.500 5.470 5.439 5.408 5.378 5.347 5.317 5.286 5.256 5.225 5.195 5.164 5.133 5.103 5.072 5.042 5.011 4.981 4.950 75mV 15 Lattice Semiconductor Table 2. Trip Point Table Used For Under-Voltage Detection Fine Range Setting 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Low-V Sense ISPPAC-POWR1014/A Data Sheet 1 0.797 0.793 0.789 0.785 0.781 0.776 0.772 0.768 0.764 0.760 0.755 0.751 0.747 0.743 0.739 0.734 0.730 0.726 0.722 0.718 0.713 0.709 0.705 0.701 0.697 0.692 0.688 0.684 0.680 0.676 0.672 2 0.950 0.945 0.940 0.935 0.930 0.925 0.920 0.915 0.910 0.905 0.900 0.895 0.890 0.885 0.880 0.875 0.870 0.865 0.860 0.855 0.850 0.845 0.840 0.835 0.830 0.825 0.820 0.815 0.810 0.805 0.800 3 1.131 1.125 1.119 1.113 1.107 1.101 1.095 1.089 1.083 1.077 1.071 1.065 1.059 1.053 1.047 1.041 1.035 1.029 1.024 1.018 1.012 1.006 1.000 0.994 0.988 0.982 0.976 0.970 0.964 0.958 0.952 4 1.346 1.338 1.331 1.324 1.317 1.310 1.303 1.296 1.289 1.282 1.275 1.268 1.261 1.254 1.246 1.239 1.232 1.225 1.218 1.211 1.204 1.197 1.190 1.183 1.176 1.169 1.161 1.154 1.147 1.140 1.133 5 1.595 1.586 1.578 1.570 1.561 1.553 1.544 1.536 1.528 1.519 1.511 1.502 1.494 1.486 1.477 1.469 1.460 1.452 1.444 1.435 1.427 1.418 1.410 1.402 1.393 1.385 1.377 1.368 1.360 1.352 - 6 1.903 1.893 1.883 1.873 1.863 1.853 1.843 1.833 1.823 1.813 1.803 1.793 1.783 1.773 1.763 1.753 1.743 1.733 1.723 1.713 1.703 1.693 1.683 1.673 1.663 1.653 1.643 1.633 1.623 1.613 1.603 7 2.266 2.254 2.242 2.230 2.219 2.207 2.195 2.183 2.171 2.159 2.147 2.135 2.123 2.111 2.099 2.087 2.075 2.063 2.052 2.040 2.028 2.016 2.004 1.992 1.980 1.968 1.956 1.944 1.932 1.920 1.908 8 2.691 2.677 2.663 2.649 2.634 2.620 2.606 2.592 2.578 2.564 2.550 2.535 2.521 2.507 2.493 2.479 2.465 2.450 2.436 2.422 2.408 2.394 2.380 2.365 2.351 2.337 2.323 2.309 2.295 2.281 2.267 9 3.190 3.173 3.156 3.139 3.122 3.106 3.089 3.072 3.055 3.038 3.022 3.005 2.988 2.971 2.954 2.938 2.921 2.904 2.887 2.871 2.854 2.837 2.820 2.803 2.787 2.770 2.753 2.736 2.719 2.702 - 10 3.799 3.779 3.759 3.739 3.719 3.699 3.679 3.659 3.639 3.619 3.599 3.579 3.559 3.539 3.519 3.499 3.479 3.459 3.439 3.419 3.399 3.379 3.359 3.339 3.319 3.299 3.279 3.259 3.239 3.219 3.199 11 4.875 4.849 4.823 4.798 4.772 4.746 4.721 4.695 4.669 4.644 4.618 4.592 4.567 4.541 4.515 4.490 4.464 4.438 4.413 4.387 4.361 4.336 4.310 4.284 4.259 4.233 4.207 4.182 4.156 4.130 4.105 12 5.806 5.775 5.745 5.714 5.683 5.653 5.622 5.592 5.561 5.531 5.500 5.470 5.439 5.408 5.378 5.347 5.317 5.286 5.256 5.225 5.195 5.164 5.133 5.103 5.072 5.042 5.011 4.981 4.950 4.919 4.889 75mV 16 Lattice Semiconductor Table 3. Comparator Hysteresis vs. Trip-Point Trip-point Range (V) Low Limit 0.672 0.800 0.952 1.133 1.346 1.603 1.908 2.267 2.691 3.199 4.105 4.889 75 mV High Limit 0.806 0.960 1.143 1.360 1.612 1.923 2.290 2.719 3.223 3.839 4.926 5.867 ISPPAC-POWR1014/A Data Sheet Hysteresis (mV) 8 10 12 14 17 20 24 28 34 40 51 61 0 (Disabled) The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA "ANDed" with COMPB signal) and a multiplexer that supports the ability to develop a `window' function without using any of the PLD's resources. Through the use of the multiplexer, voltage monitor's `A' output may be set to report either the status of the `A' comparator, or the window function of both comparator outputs. The voltage monitor's `A' output indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing function is only valid in cases where the threshold of the `A' comparator is set to a value higher than that of the `B' comparator. Table 4 shows the operation of window function logic. Table 4. Voltage Monitor Windowing Logic Input Voltage VIN < Trip-point B < Trip-point A Trip-point B < VIN < Trip-point A Trip-point B < Trip-point A < VIN Comp A 0 0 1 Comp B 0 1 1 Window (B and Not A) 0 1 0 Comment Outside window, low Inside window Outside window, high Note that when the `A' output of the voltage monitor circuit is set to windowing mode, the `B' output continues to monitor the output of the `B' comparator. This can be useful in that the `B' output can be used to augment the windowing function by determining if the input is above or below the windowing range. The third section in the ISPPAC-POWR1014/A's input voltage monitor is a digital filter. When enabled, the comparator output will be delayed by a filter time constant of 64 s, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16s. In both cases, enabled or disabled, the filters also provide synchronization of the input signals to the PLD clock. This synchronous sampling feature effectively eliminates the possibility of race conditions from occurring in any subsequent logic that is implemented in the ISPPAC-POWR1014/A's internal PLD logic. The comparator status can be read from the I2C interface (ISPPAC-POWR1014A only). For details on the I2C interface, please refer to the I2C/SMBUS Interface section of this data sheet. 17 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet VMON Voltage Measurement with the On-chip Analog to Digital Converter (ADC, ispPACPOWR1014A Only) The ISPPAC-POWR1014A has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON inputs. Figure 8. ADC Monitoring VMON1 to VMON10 VMON1 VMON2 VMON3 Programmable Digital Multiplier Programmable Analog Attenuator ADC MUX /3 / /1 ADC x3 / x1 10 12 To I2C Readout Register (ISPPAC-POWR1014A Only) VMON10 VDDA VCCINP 4 5 1 Internal VREF- 2.048V From I 2 C ADC MUX Register (ISPPAC-POWR1014A Only) Figure 8 shows the ADC circuit arrangement within the ISPPAC-POWR1014A device. The ADC can measure all analog input voltages through the multiplexer, ADC MUX. The programmable attenuator between the ADC mux and the ADC can be configured as divided-by-3 or divided-by-1 (no attenuation). The divided-by-3 setting is used to measure voltages from 0V to 6V range and divided-by-1 setting is used to measure the voltages from 0V to 2V range. A microcontroller can place a request for any VMON voltage measurement at any time through the I2C bus (ISPPAC-POWR1014A only). Upon the receipt of an I2C command, the ADC will be connected to the I2C selected VMON through the ADC MUX. The ADC output is then latched into the I2C readout registers. Calculation The algorithm to convert the ADC code to the corresponding voltage takes into consideration the attenuation bit value. In other words, if the attenuation bit is set, then the 10-bit ADC result is automatically multiplied by 3 to calculate the actual voltage at that VMON input. Thus, the I2C readout register is 12 bits instead of 10 bits. The following formula can always be used to calculate the actual voltage from the ADC code. Voltage at the VMONx Pins VMON = I2C Readout Register (12 bits1, converted to decimal) * 2mV 1 Note: ADC_VALUE_HIGH (8 bits), ADC_VALUE_LOW (4 bits) read from I2C/SMBUS interface (ISPPAC-POWR1014A only). 18 Lattice Semiconductor PLD Block ISPPAC-POWR1014/A Data Sheet Figure 9 shows the ISPPAC-POWR1014/A PLD architecture, which is derived from the Lattice's ispMACHTM 4000 CPLD. The PLD architecture allows the flexibility in designing various state machines and control functions used for power supply management. The AND array has 53 inputs and generates 123 product terms. These 123 product terms are divided into three groups of 41 for each of the generic logic blocks, GLB1, GLB2, and GLB3. Each GLB is made up of eight macrocells. In total, there are 24 macrocells in the ISPPAC-POWR1014/A device. The output signals of the ISPPAC-POWR1014/A device are derived from GLBs as shown in Figure 9. GLB3 generates timer control. Figure 9. ISPPAC-POWR1014/A PLD Architecture Global Reset (Resetb pin) AGOOD 41 GLB1 Generic Logic Block 8 Macrocell 41 PT HVOUT[1..2], OUT[3..8] IN[1:4] 4 VMON[1-10] 20 AND Array 53 Inputs 123 PT 41 GLB2 Generic Logic Block 8 Macrocell 41 PT OUT[9..14] 4 Output Feedback 41 GLB3 Generic Logic Block 8 Macrocell 41 PT 24 Timer0 Timer1 Timer2 Timer3 IRP 18 Timer Clock PLD Clock Macrocell Architecture The macrocell shown in Figure 10 is the heart of the PLD. The basic macrocell has five product terms that feed the OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. The polarity control and XOR gates provide additional flexibility for logic synthesis. The flip-flop's clock is driven from the common PLD clock that is generated by dividing the 8 MHz master clock by 32. The macrocell also supports asynchronous reset and preset functions, derived from either product terms, the global reset input, or the power-on reset signal. The resources within the macrocells share routing and contain a product term allocation array. The product term allocation array greatly expands the PLD's ability to implement complex logical functions by allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. 19 Lattice Semiconductor Figure 10. ISPPAC-POWR1014/A Macrocell Block Diagram Global Reset Global Polarity Fuse for Init Product Term Block Init Product Term ISPPAC-POWR1014/A Data Sheet Power On Reset Product Term Allocation PT4 PT3 PT2 PT1 PT0 R D/T P Q To PLD Output Polarity CLK Clock Macrocell flip-flop provides D, T, or combinatorial output with polarity Clock and Timer Functions Figure 11 shows a block diagram of the ISPPAC-POWR1014/A's internal clock and timer systems. The master clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived. Figure 11. Clock and Timer System PLD Clock Timer 0 Internal Oscillator 8MHz SW0 32 Timer 1 To/From PLD Timer 2 SW1 Timer 3 SW2 MCLK PLDCLK The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer clocks. It is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir- 20 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet cuits and ADC. The ISPPAC-POWR1014/A can be programmed to operate in three modes: Master mode, Standalone mode and Slave mode. Table 5 summarizes the operating modes of ISPPAC-POWR1014/A. Table 5. ISPPAC-POWR1014/A Operating Modes Timer Operating Mode Standalone Master SW0 Closed Closed SW1 Open Closed Condition When only one ISPPAC-POWR1014/A is used. Comments MCLK pin tristated When more than one ISPPAC-POWR1014/A is used in a board, one of them should be configured MCLK pin outputs 8MHz clock to operate in this mode. When more than one ISPPAC-POWR1014/As is used in a board. Other than the master, the rest of MCLK pin is input the ISPPAC-POWR1014/As should be programmed as slaves. Slave Open Closed A divide-by-32 prescaler divides the internal 8MHz oscillator (or external clock, if selected) down to 250kHz for the PLD clock and for the programmable timers. This PLD clock may be made available on the PLDCLK pin by closing SW2. Each of the four timers provides independent timeout intervals ranging from 32s to 1.96 seconds in 128 steps. Digital Outputs The ISPPAC-POWR1014/A provides 14 digital outputs, HVOUT[1:2] and OUT[3:14]. Outputs OUT[3:14] are permanently configured as open drain to provide a high degree of flexibility when interfacing to logic signals, LEDs, optocouplers, and power supply control inputs. The HVOUT[1:2] pins can be configured as either high voltage FET drivers or open drain outputs. Each of these outputs may be controlled either from the PLD or from the I2C bus (ISPPAC-POWR1014A only). The determination whether a given output is under PLD or I2C control may be made on a pin-by-pin basis (see Figure 12). For further details on controlling the outputs through I2C, please see the I2C/ SMBUS Interface section of this data sheet. Figure 12. Digital Output Pin Configuration Digital Control from PLD OUTx Pin Digital Control from I2C Register (ISPPAC-POWR1014A only) High-Voltage Outputs In addition to being usable as digital open-drain outputs, the ISPPAC-POWR1014/A's HVOUT1-HVOUT2 output pins can be programmed to operate as high-voltage FET drivers. Figure 13 shows the details of the HVOUT gate drivers. Each of these outputs may be controlled from the PLD, or with the ISPPAC-POWR1014A, from the I2C bus (see Figure 13). For further details on controlling the outputs through I2C, please see the I2C/SMBUS Interface section of this data sheet. 21 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Figure 13. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode Charge Pump (6 to 10V) ISOURCE (12.5 to 100 A) Input Supply + - HVOUTx Pin Digital Control from PLD ISINK (100 to 500 A) +Fast Turn-off (3000A) Load Digital Control from I2C Register (ISPPAC-POWR1014A Only) Figure 13 shows the HVOUT circuitry when programmed as a FET driver. In this mode the output either sources current from a charge pump or sinks current. The maximum voltage that the output level at the pin will rise to is also programmable between 6V and 10V. The maximum voltage levels that are required depend on the gate-to-source threshold of the FET being driven and the power supply voltage being switched. The maximum voltage level needs to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the FET's source, since the source pin of the FET to provide a wide range of ramp rates is tied to the supply of the target board. When the HVOUT pin is sourcing current, charging a FET gate, the source current is programmable between 12.5A and 100A. When the driver is turned to the off state, the driver will sink current to ground, and this sink current is also programmable between 3000A and 100A to control the turn-off rate. Programmable Output Voltage Levels for HVOUT1- HVOUT2 There are three selectable steps for the output voltage of the FET drivers when in FET driver mode. The voltage that the pin is capable of driving to can be programmed from 6V to 10V in 2V steps. RESETb Signal, RESET Command via JTAG or I2C Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG, or with the ISPPAC-POWR1014A, I2C will force the outputs to the following states independent of how these outputs have been configured in the PINS window: * OUT3-14 will go high-impedance. * HVOUT pins programmed for open drain operation will go high-impedance. * HVOUT pins programmed for FET driver mode operation will pull down. At the conclusion of the RESET event, these outputs will go to the states defined by the PINS window, and if a sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be re-done and consequently, the VMONs, and ADCs will not be operational until 500 microseconds (max.) after the conclusion of the RESET event. CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the ispPACPOWR1014/A device operation, results in the device aborting all operations and returning to the power-on reset state. The status of the power supplies which are being enabled by the ISPPAC-POWR1014/A will be determined by the state of the outputs shown above. 22 Lattice Semiconductor I2C/SMBUS Interface (ISPPAC-POWR1014A Only) ISPPAC-POWR1014/A Data Sheet I2C and SMBus are low-speed serial interface protocols designed to enable communications among a number of devices on a circuit board. The ISPPAC-POWR1014A supports a 7-bit addressing of the I2C communications protocol, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types of modern power management systems. Figure 14 shows a typical I2C configuration, in which one or more ispPACPOWR1014As are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I2C address of the POWR1014A is fully programmable through the JTAG port. Figure 14. ISPPAC-POWR1014A in I 2C/SMBUS System V+ SDA/SMDAT (DATA) SCL/SMCLK (CLOCK) SMBALERT To Other I2C Devices SDA SCL INTERRUPT SDA SCL OUT5/ SMBA SDA SCL OUT5/ SMBA MICROPROCESSOR (I2C MASTER) POWR1014A (I2C SLAVE) POWR1014A (I2C SLAVE) In both the I2C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This master device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices. The ISPPAC-POWR1014A is configured as a slave device, and cannot independently coordinate data transfers. Each slave device on a given I2C bus is assigned a unique address. The ISPPAC-POWR1014A implements the 7-bit addressing portion of the standard. Any 7-bit address can be assigned to the ISPPAC-POWR1014A device by programming through JTAG. When selecting a device address, one should note that several addresses are reserved by the I2C and/or SMBus standards, and should not be assigned to ISPPAC-POWR1014A devices to assure bus compatibility. Table 6 lists these reserved addresses. Table 6. I 2C/SMBus Reserved Slave Device Addresses Address 0000 000 0000 000 0000 001 0000 010 0000 011 0000 1xx 0001 000 0001 100 0101 000 0110 111 1100 001 1111 0xx 1111 1xx R/W bit 0 1 x x x x x x x x x x x I2C function Description General Call Address Start Byte CBUS Address Reserved Reserved HS-mode master code NA NA NA NA NA 10-bit addressing Reserved Start Byte CBUS Address Reserved Reserved HS-mode master code SMBus Host SMBus Alert Response Address Reserved for ACCESS.bus Reserved for ACCESS.bus SMBus Device Default Address 10-bit addressing Reserved SMBus Function General Call Address 23 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet The ISPPAC-POWR1014A's I2C/SMBus interface allows data to be both written to and read from the device. A data write transaction (Figure 15) consists of the following operations: 1. Start the bus transaction 2. Transmit the device address (7 bits) along with a low write bit 3. Transmit the address of the register to be written to (8 bits) 4. Transmit the data to be written (8 bits) 5. Stop the bus transaction To start the transaction, the master device holds the SCL line high while pulling SDA low. Address and data bits are then transferred on each successive SCL pulse, in three consecutive byte frames of 9 SCL pulses. Address and data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format. The first frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. The second frame contains the register address to which data will be written, and the final frame contains the actual data to be written. Note that the SDA signal is only allowed to change when the SCL is low, as raising SDA when SCL is high signals the end of the transaction. Figure 15. I 2C Write Operation SCL SDA START 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/W 9 ACK 1 R7 2 R6 3 R5 4 R4 5 R3 6 R2 7 R1 8 R0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK DEVICE ADDRESS (7 BITS) REGISTER ADDRESS (8 BITS) WRITE DATA (8 BITS) STOP Note: Shaded Bits Asserted by Slave Reading a data byte from the ISPPAC-POWR1014A requires two separate bus transactions (Figure 16). The first transaction writes the register address from which a data byte is to be read. Note that since no data is being written to the device, the transaction is concluded after the second byte frame. The second transaction performs the actual read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the ispPACPOWR1014A asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the ISPPAC-POWR1014A. Figure 16. I 2C Read Operation STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION SCL SDA START 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/W 9 ACK 1 R7 2 R6 3 R5 4 R4 5 R3 6 R2 7 R1 8 R0 9 ACK DEVICE ADDRESS (7 BITS) REGISTER ADDRESS (8 BITS) STOP STEP 2: READ DATA FROM THAT REGISTER SCL SDA START 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/W 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK DEVICE ADDRESS (7 BITS) READ DATA (8 BITS) OPTIONAL STOP Note: Shaded Bits Asserted by Slave The ISPPAC-POWR1014A provides 17 registers that can be accessed through its I2C interface. These registers provide the user with the ability to monitor and control the device's inputs and outputs, and transfer data to and from the device. Table 7 provides a summary of these registers. 24 Lattice Semiconductor Table 7. I 2C Control Registers Register Address 0x00 0x01 0x02 0x03 0x04 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x11 0x12 Register Name vmon_status0 vmon_status1 vmon_status2 output_status0 output_status1 input_status adc_value_low adc_value_high adc_mux UES_byte0 UES_byte1 UES_byte2 UES_byte3 gp_output1 gp_output2 input_value reset Read/Write R R R R R R R R R/W R R R R R/W R/W R/W W Description VMON input status Vmon[4:1] VMON input status Vmon[8:5] ISPPAC-POWR1014/A Data Sheet Value After POR1, 2 ---- ---- ---- ---- XXXX ---- ---- ---- XX-- ---- XXXX ---- ---- XXX1 XX-- ---- XXX1 1111 ---- ---- ---- ---- ---- ---- ---- ---- 0000 0100 XX00 0000 XXXX ---X N/A VMON input status Vmon[10:9] Output status OUT[8:3], HVOUT[2:1] Output status OUT[14:9] Input status IN[4:1] ADC D[3:0] and status ADC D[9:4] ADC Attenuator and MUX[3:0] UES[7:0] UES[15:8] UES[23:16] UES[31:24] GPOUT[8:1] GPOUT[14:9] PLD Input State [4:2] Resets device on write 1. "X" = Non-functional bit (bits read out as 1's). 2. "-" = State depends on device configuration or input status. Several registers are provided for monitoring the status of the analog inputs. The three registers VMON_STATUS[0:2] provide the ability to read the status of the VMON output comparators. The ability to read both the `a' and `b' comparators from each VMON input is provided through the VMON input registers. Note that if a VMON input is configured to window comparison mode, then the corresponding VMONxA register bit will reflect the status of the window comparison. Figure 17. VMON Status Registers 0x00 - VMON_STATUS0 (Read Only) VMON4B b7 VMON4A b6 VMON3B b5 VMON3A b4 VMON2B b3 VMON2A b2 VMON1B b1 VMON1A b0 0x01 - VMON_STATUS1 (Read Only) VMON8B b7 VMON8A b6 VMON7B b5 VMON7A b4 VMON6B b3 VMON6A b2 VMON5B b1 VMON5A b0 0x02 - VMON_STATUS2 (Read Only) 1 b7 1 b6 1 b5 1 b4 VMON10B b3 VMON10A b2 VMON9B b1 VMON9A b0 It is also possible to directly read the value of the voltage present on any of the VMON inputs by using the ispPACPOWR1014A's ADC. Three registers provide the I2C interface to the ADC (Figure 18). 25 Lattice Semiconductor Figure 18. ADC Interface Registers 0x07 - ADC_VALUE_LOW (Read Only) D3 b7 D2 b6 D1 b5 D0 b4 1 b3 ISPPAC-POWR1014/A Data Sheet 1 b2 1 b1 DONE b0 0x08 - ADC_VALUE_HIGH (Read Only) D11 b7 D10 b6 D9 b5 D8 b4 D7 b3 D6 b2 D5 b1 D4 b0 0x09 - ADC_MUX (Read/Write) X b7 X b6 X b5 ATTEN b4 SEL3 b3 SEL2 b2 SEL1 b1 SEL0 b0 To perform an A/D conversion, one must set the input attenuator and channel selector. Two input ranges may be set using the attenuator, 0 - 2.048V and 0 - 6.144V. Table 8 shows the input attenuator settings. Table 8. ADC Input Attenuator Control ATTEN (ADC_MUX.4) 0 1 Resolution 2mV 6mV Full-Scale Range 2.048 V 6.144 V The input selector may be set to monitor any one of the ten VMON inputs, the VCCA input, or the VCCINP input. Table 9 shows the codes associated with each input selection. Table 9. VMON Address Selection Table Select Word SEL3 (ADC_MUX.3) 0 0 0 0 0 0 0 0 1 1 1 1 SEL2 (ADC_MUX.2) 0 0 0 0 1 1 1 1 0 0 1 1 SEL1 (ADC_MUX.1) 0 0 1 1 0 0 1 1 0 0 0 0 SEL0 (ADC_MUX.0) 0 1 0 1 0 1 0 1 0 1 0 1 Input Channel VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 VCCA VCCINP Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conversion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conversion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by performing two I2C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recommended that the I2C master load a second conversion command only after the completion of the current conversion 26 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time (see TCONVERT value in the specifications) and disregard checking the DONE bit. Note that if the I2C clock rate falls below 50kHz (see FI2C note in specifications), the only way to insure a valid ADC conversion is to wait the minimum specified time (TCONVERT), as the operation of the DONE bit at clock rates lower than that cannot be guaranteed. In other words, if the I2C clock rate is less than 50kHz, the DONE bit may or may not assert even though a valid conversion result is available. To insure every ADC conversion result is valid, preferred operation is to clock I2C at more than 50kHz and verify DONE bit status or wait for the full TCONVERT time period between subsequent ADC convert commands. If an I2C request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second request is complete. The status of the digital input lines may also be monitored and controlled through I2C commands. Figure 19 shows the I2C interface to the IN[1:4] digital input lines. The input status may be monitored by reading the INPUT_STATUS register, while input values to the PLD array may be set by writing to the INPUT_VALUE register. To be able to set an input value for the PLD array, the input multiplexer associated with that bit needs to be set to the I2C register setting in E2CMOS memory otherwise the PLD will receive its input from the INx pin. Figure 19. I 2C Digital Input Interface PLD Output/Input_Value Register Select (E2 Configuration) 3 IN1 USERJTAG Bit IN[2..4] 3 MUX 2 PLD Array MUX 3 3 Input_Value Input_Status I2C Interface Unit 0x06 - INPUT_STATUS (Read Only) 1 b7 1 b6 1 b5 1 b4 IN4 b3 IN3 b2 IN2 b1 IN1 b0 0x11 - INPUT_VALUE (Read/Write) X b7 X b6 X b5 X b4 I4 I3 I2 X b3 b2 b1 b0 The digital outputs may also be monitored and controlled through the I2C interface, as shown in Figure 20. The status of any given digital output may be read by reading the contents of the associated OUTPUT_STATUS[1:0] register. Note that in the case of the outputs, the status reflected by these registers reflects the logic signal used to drive the pin, and does not sample the actual level present on the output pin. For example, if an output is set high but is 27 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet not pulled up, the output status bit corresponding with that pin will read `1', but a high output signal will not appear on the pin. Digital outputs may also be optionally controlled directly by the I2C bus instead of by the PLD array. The outputs may be driven either from the PLD output or from the contents of the GP_OUTPUT[1:0] registers with the choice user-settable in E2CMOS memory. Each output may be independently set to output from the PLD or from the GP_OUTPUT registers. Figure 20. I 2C Output Monitor and Control Logic PLD Output/GP_Output Register Select (E2 Configuration) PLD Output Routing Pool 14 14 MUX 14 14 14 HVOUT[1..2] OUT[3..14] GP_Output1 GP_Output2 Output_Status0 Output_Status1 I2C Interface Unit 0x03 - OUTPUT_STATUS0 (Read Only) OUT8 b7 OUT7 b6 OUT6 b5 OUT5 b4 OUT4 b3 OUT3 b2 HVOUT2 b1 HVOUT1 b0 0x04 - OUTPUT_STATUS1 (Read Only) 1 b7 1 b6 OUT14 b5 OUT13 b4 OUT12 b3 OUT11 b2 OUT10 b1 OUT9 b0 0x0E - GP_OUTPUT1 (Read/Write) GP8 b7 GP7 b6 GP6 b5 GP5 b4 GP4 b3 GP3_ENb b2 GP2 b1 GP1 b0 0x0F - GP_OUTPUT2 (Read/Write) X b7 X b6 GP14 b5 GP13 b4 GP12 b3 GP11 b2 GP10 b1 GP9 b0 The UES word may also be read through the I2C interface, with the register mapping shown in Figure 21. 28 Lattice Semiconductor Figure 21. I 2C Register Mapping for UES Bits 0x0A - UES_BYTE0 (Read Only) UES7 b7 UES6 b6 UES5 b5 UES4 b4 UES3 b3 ISPPAC-POWR1014/A Data Sheet UES2 b2 UES1 b1 UES0 b0 0x0B - UES_BYTE1 (Read Only) UES15 b7 UES14 b6 UES13 b5 UES12 b4 UES11 b3 UES10 b2 UES9 b1 UES8 b0 0x0C - UES_BYTE2 (Read Only) UES23 b7 UES22 b6 UES21 b5 UES20 b4 UES19 b3 UES18 b2 UES17 b1 UES16 b0 0x0D - UES_BYTE3 (Read Only) UES31 b7 UES30 b6 UES29 b5 UES28 b4 UES27 b3 UES26 b2 UES25 b1 UES24 b0 The I2C interface also provides the ability to initiate reset operations. The ISPPAC-POWR1014A may be reset by issuing a write of any value to the I2C RESET register (Figure 22). Note: The execution of the I2C reset command is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I2C section of this data sheet for further information. Figure 22. I 2C Reset Register 0x12 - RESET (Write Only) X b7 X b6 X b5 X b4 X b3 X b2 X b1 X b0 29 Lattice Semiconductor SMBus SMBAlert Function ISPPAC-POWR1014/A Data Sheet The ISPPAC-POWR1014A provides an SMBus SMBAlert function so that it can request service from the bus master when it is used as part of an SMBus system. This feature is supported as an alternate function of OUT3. When the SMBAlert feature is enabled, OUT3 is controlled by a combination of the PLD output and the GP3_ENb bit (Figure 23). Note: To enable the SMBAlert feature, the SMB_Mode (EECMOS bit) should be set in software. Figure 23. ISPPAC-POWR1014/A SMBAlert Logic PLD Output/GP_Output Register Select (E2 Configuration) OUT3/SMBA Mode Select (E2 Configuration) PLD Output Routing Pool MUX MUX OUT3/SMBA GP3_ENb SMBAlert Logic I2C Interface Unit The typical flow for an SMBAlert transaction is as follows (Figure 23): 1. GP3_ENb bit is forced (Via I2C write) to Low 2. ISPPAC-POWR1014A PLD Logic pulls OUT3/SMBA Low 3. Master responds to interrupt from SMBA line 4. Master broadcasts a read operation using the SMBus Alert Response Address (ARA) 5. ISPPAC-POWR1014A responds to read request by transmitting its device address 6. If transmitted device address matches ISPPAC-POWR1014A address, it sets GP3_ENb bit high. This releases OUT3/SMBA. Figure 24. SMBAlert Bus Transaction SMBA SCL SDA SLAVE ASSERTS SMBA START 1 0 2 0 3 0 4 1 5 1 6 0 7 0 8 R/W 9 ACK 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 x 9 ACK ALERT RESPONSE ADDRESS (0001 100) SLAVE ADDRESS (7 BITS) SLAVE RELEASES SMBA STOP Note: Shaded Bits Asserted by Slave After OUT3/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the ISPPAC-POWR1014A. As part of the service functions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset GP3_ENb to re-enable the SMBAlert function. For further information on the SMBus, the user should consult the SMBus Standard. 30 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Software-Based Design Environment Designers can configure the ISPPAC-POWR1014/A using PAC-Designer, an easy to use, Microsoft Windows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the ISPPAC-POWR1014/A. A library of configurations is included with basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading. In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 25, provides access to all configurable ispPACPOWR1014/A elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, configurations can be saved, simulated, and downloaded to devices. Figure 25. PAC-Designer ISPPAC-POWR1014/A Design Entry Screen In-System Programming The ISPPAC-POWR1014/A is an in-system programmable device. This is accomplished by integrating all E2 configuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPACPOWR1014/A instructions are described in the JTAG interface section of this data sheet. Programming ISPPAC-POWR1014/A: Alternate Method Some applications require that the ISPPAC-POWR1014/A be programmed before turning the power on to the entire circuit board. To meet such application needs, the ISPPAC-POWR1014/A provides an alternate programming method which enables the programming of the ISPPAC-POWR1014/A device through the JTAG chain with a separate power supply applied just to the programming section of the ISPPAC-POWR1014/A device with the main power supply of the board turned off. 31 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Three special purpose pins, VCCPROG, ATDI and TDISEL, enable programming of the un-programmed ispPACPOWR1014/A under such circumstances. The VCCPROG pin powers just the programming circuitry of the ispPACPOWR1014/A device. The ATDI pin provides an alternate connection to the JTAG header while bypassing all the un-powered devices in the JTAG chain. TDISEL pin enables switching between the ATDI and the standard JTAG signal TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI is enabled. In order to use this feature the JTAG signals of the ISPPAC-POWR1014/A are connected to the header as shown in Figure 26. Note: The ISPPAC-POWR1014/A should be the last device in the JTAG chain. Figure 26. ISPPAC-POWR1014/A Alternate TDI Configuration Diagram 1. Power for Programming POWR1014A 3. Sequenced Power Supply Turn-on 2. Initial Power Supply Turn-On VCCPROG VCCIO VCCJ VCCJ VCC VCC JTAG Signal Connector TDI TDI Other JTAG Device(s) TDO TDI ispPAC-POWR 1014A TDO ATDI TCK TMS TCK TMS TDISEL TCK TMS TDO TDISEL Alternate TDI Selection Via JTAG Command When the TDISEL pin held high and four consecutive IDCODE instructions are issued, ISPPAC-POWR1014/A responds by making its active JTAG data input the ATDI pin. When ATDI is selected, data on its TDI pin is ignored until the JTAG state machine returns to the Test-Logic-Reset state. This method of selecting ATDI takes advantage of the fact that a JTAG device with an IDCODE register will automatically load its unique IDCODE instruction into the Instruction Register after a Test-Logic-Reset. This JTAG capability permits blind interrogation of devices so that their location in a serial chain can be identified without having to know anything about them in advance. A blind interrogation can be made using only the TMS and TCLK control pins, which means TDI and TDO are not required for performing the operation. Figure 27 illustrates the logic for selecting whether the TDI or ATDI pin is the active data input to ISPPAC-POWR1014/A. 32 Lattice Semiconductor Figure 27. ISPPAC-POWR1014/A TDI/ATDI Pin Selection Diagram TMS TCK ISPPAC-POWR1014/A Data Sheet TDI ATDI 1 JTAG 0 Test-Logic-Reset 4 Consecutive IDCODE Instructions Loaded at Update-IR TDO TDISEL SET Q CLR ISPPAC-POWR1014/A Table 10 shows in truth table form the same conditions required to select either TDI or ATDI as in the logic diagram found in Figure 27. Table 10. ISPPAC-POWR1014/A ATDI/TDI Selection Table JTAG State Machine Test-Logic-Reset No Yes X 4 Consecutive IDCODE Commands Loaded at Update-IR Yes No X Active JTAG Data Input Pin ATDI (TDI Disabled) TDI (ATDI Disabled) ATDI (TDI Disabled) TDISEL Pin H H L Please refer to the Lattice application note AN6068, Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using ATDI. The application note includes specific SVF code examples and information on the use of Lattice design tools to verify device operation in alternate TDI mode. VCCPROG Power Supply Pin Because the VCCPROG pin directly powers the on-chip programming circuitry, the ISPPAC-POWR1014/A device can be programmed by applying power to the VCCPROG pin (without powering the entire chip though the VCCD and VCCA pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin. When the ISPPAC-POWR1014/A is using the VCCPROG pin, its VCCD and VCCA pins can be open or pulled low. Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOSFET driver are driven low, and all other inputs are ignored. To switch the power supply back to VCCD and VCCA pins, one should turn the VCCPROG supply and VCCJ off before turning the regular supplies on. User Electronic Signature A user electronic signature (UES) feature is included in the E2CMOS memory of the ISPPAC-POWR1014/A. This consists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or 33 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet inventory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet. Electronic Security An electronic security "fuse" (ESF) bit is provided in every ISPPAC-POWR1014/A device to prevent unauthorized readout of the E2CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased by reprogramming the device, so the original configuration cannot be examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet. Production Programming Support Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer software. Devices can then be ordered through the usual supply channels with the user's specific configuration already preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and flexibility in production planning. Evaluation Fixture Because the features of an ISPPAC-POWR1014/A are all included in the larger ispPAC-POWR1220AT8 device, designs implemented in an ISPPAC-POWR1014/A can be verified using an ispPAC-POWR1220AT8 engineering prototype board connected to the parallel port of a PC with a Lattice ispDOWNLOAD(R) cable. The board demonstrates proper layout techniques and can be used in real time to check circuit operation as part of the design process. Input and output connections are provided to aid in the evaluation of the functionality implemented in ispPACPOWR1014/A for a given application. (Figure 28). Figure 28. Download from a PC PAC-Designer Software Other System Circuitry ispDOWNLOAD Cable (6') 4 ispPAC-POWR 1220AT8 Device IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ISPPAC-POWR1014/A is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the ISPPAC-POWR1014/A as a serial programming interface. A brief description of the ISPPAC-POWR1014/A JTAG interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now includes IEEE Std 1149.1a-1993). Overview An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the ISPPAC-POWR1014/A. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. Device programming is performed by addressing the configuration register, shifting data in, and then executing a program configuration instruction, after which the data is transferred to internal E2CMOS cells. It is these non-volatile cells that store the configuration or the ISPPAC-POWR1014/A. A set of 34 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet instructions are defined that access all data registers and perform other internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 29 shows how the instruction and various data registers are organized in an ISPPAC-POWR1014/A. Figure 29. ISPPAC-POWR1014/A TAP Registers DATA REGISTER (123 BITS) E2CMOS NON-VOLATILE MEMORY ADDRESS REGISTER (109 BITS) UES REGISTER (32 BITS) MULTIPLEXER IDCODE REGISTER (32 BITS) CFG ADDRESS REGISTER (12 BITS) CFG DATA REGISTER (56 BITS) BYPASS REGISTER (1 BIT) INSTRUCTION REGISTER (8 BITS) TEST ACCESS PORT (TAP) LOGIC OUTPUT LATCH TDI TCK TMS TDO TAP Controller Specifics The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as shown in Figure 30. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, RunTest/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state. 35 Lattice Semiconductor Figure 30. TAP States 1 0 Test-Logic-Rst 0 Run-Test/Idle 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 0 1 Exit2-DR 1 Update-DR 1 0 0 0 1 1 ISPPAC-POWR1014/A Data Sheet Select-IR-Scan 1 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 0 1 Exit2-IR 1 Update-IR 1 0 1 0 1 0 Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction shift is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruction shift is performed. The states of the Data and Instruction Register blocks are identical to each other differing only in their entry points. When either block is entered, the first action is a capture operation. For the Data Registers, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a "blind" interrogation of any device in a compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction Register while an external operation is performed. From the Pause state, shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state. Test Instructions Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the function of three required and six optional instructions. Any additional instructions are left exclusively for the manufacturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respectively). The ISPPAC-POWR1014/A contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and verified. Table 11 lists the instructions supported by the ISPPAC-POWR1014/A JTAG Test Access Port (TAP) controller: 36 Lattice Semiconductor Table 11. ISPPAC-POWR1014/A TAP Instruction Table Instruction BULK_ERASE BYPASS DISCHARGE ERASE_DONE_BIT EXTEST IDCODE OUTPUTS_HIGHZ SAMPLE/PRELOAD PROGRAM_DISABLE PROGRAM_DONE_BIT PROGRAM_ENABLE PROGRAM_SECURITY RESET IN1_RESET_JTAG_BIT IN1_SET_JTAG_BIT CFG_ADDRESS CFG_DATA_SHIFT CFG_ERASE CFG_PROGRAM CFG_VERIFY PLD_ADDRESS_SHIFT PLD_DATA_SHIFT PLD_INIT_ADDR_FOR_PROG_INCR PLD_PROG_INCR PLD_PROGRAM PLD_VERIFY PLD_VERIFY_INCR UES_PROGRAM UES_READ Command Code 0000 0011 1111 1111 0001 0100 0010 0100 0000 0000 0001 0110 0001 1000 00011100 0001 1110 0010 1111 0001 0101 0000 1001 0010 0010 0001 0010 0001 0011 0010 1011 0010 1101 0010 1001 0010 1110 0010 1000 0000 0001 0000 0010 0010 0001 0010 0111 0000 0111 0000 1010 0010 1010 0001 1010 0001 0111 Bulk erase device ISPPAC-POWR1014/A Data Sheet Comments Bypass - connect TDO to TDI Fast VPP discharge Erases `Done' bit only Bypass - connect TDO to TDI Read contents of manufacturer ID code (32 bits) Force all outputs to High-Z state, FET outputs pulled low Sample/Preload. Default to bypass. Disable program mode Programs the Done bit Enable program mode Program security fuse Resets device (refer to the RESETb Signal, RESET Command via JTAG or I2C section of this data sheet) Reset the JTAG bit associated with IN1 pin to 0 Set the JTAG bit associated with IN1 pin to 1 Select non-PLD address register Non-PLD data shift ERASE Just the Non PLD configuration Non-PLD program VRIFY non-PLD fusemap data PLD_Address register (109 bits) PLD_Data register (123 Bits) Initialize the address register for auto increment Program column register to E2 and auto increment address register Program PLD data register to E2 Verifies PLD column data Load column register from E2 and auto increment address register Program UES bits into E2 Read contents of UES register from E2 (32 bits) BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPACPOWR1014/A. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ISPPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 11. The EXTEST (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the ISPPAC-POWR1014/A has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000). 37 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet The optional IDCODE (identification code) instruction is incorporated in the ISPPAC-POWR1014/A and leaves it in its functional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type and version code (Figure 31). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 11. Figure 31. ISPPAC-POWR1014/A ID Code MSB LSB (ISPPAC-POWR1014) (ISPPAC-POWR1014A) 0001 0000 0001 0100 0101 / 0000 0100 001 / 1 0000 0000 0001 0100 0101 / 0000 0100 001 / 1 Part Number (20 bits) 00145h = ISPPAC-POWR1014A 10145h = ISPPAC-POWR1014 JEDEC Manufacturer Identity Code for Lattice Semiconductor (11 bits) Constant 1 (1 bit) per 1149.1-1990 ISPPAC-POWR1014/A Specific Instructions There are 25 unique instructions specified by Lattice for the ISPPAC-POWR1014/A. These instructions are primarily used to interface to the various user registers and the E2CMOS non-volatile memory. Additional instructions are used to control or monitor other features of the device. A brief description of each unique instruction is provided in detail below, and the bit codes are found in Table 11. PLD_ADDRESS_SHIFT - This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ. PLD_DATA_SHIFT - This instruction is used to shift PLD data into the register prior to programming or reading. This instruction also forces the outputs into the OUTPUTS_HIGHZ. PLD_INIT_ADDR_FOR_PROG_INCR - This instruction prepares the PLD address register for subsequent PLD_PROG_INCR or PLD_VERIFY_INCR instructions. PLD_PROG_INCR - This instruction programs the PLD data register for the current address and increments the address register for the next set of data. PLD_PROGRAM - This instruction programs the selected PLD AND/ARCH array column. The specific column is preselected by using PLD_ADDRESS_SHIFT instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. PROGRAM_SECURITY - This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. PLD_VERIFY - This instruction is used to read the content of the selected PLD AND/ARCH array column. This specific column is preselected by using PLD_ADDRESS_SHIFT instruction. This instruction also forces the outputs into the OUTPUTS_HIGHZ. DISCHARGE - This instruction is used to discharge the internal programming supply voltage after an erase or programming cycle and prepares ISPPAC-POWR1014/A for a read cycle. This instruction also forces the outputs into the OUTPUTS_HIGHZ. 38 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet CFG_ADDRESS - This instruction is used to set the address of the CFG array for subsequent program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_DATA_SHIFT - This instruction is used to shift data into the CFG register prior to programming or reading. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_ERASE - This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_PROGRAM - This instruction programs the selected CFG array column. This specific column is preselected by using CFG_ADDRESS instruction. The programming occurs at the second rising edge of the TCK in Run-TestIdle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_VERIFY - This instruction is used to read the content of the selected CFG array column. This specific column is preselected by using CFG_ADDRESS instruction. This instruction also forces the outputs into the OUTPUTS_HIGHZ. BULK_ERASE - This instruction will bulk erase all E2CMOS bits (CFG, PLD, UES, and ESF) in the ispPACPOWR1014/A. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. OUTPUTS_HIGHZ - This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG state. PROGRAM_ENABLE - This instruction enables the programming mode of the ISPPAC-POWR1014/A. This instruction also forces the outputs into the OUTPUTS_HIGHZ. IDCODE - This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO (Figure 32), to support reading out the identification code. Figure 32. IDCODE Register TDO Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PROGRAM_DISABLE - This instruction disables the programming mode of the ISPPAC-POWR1014/A. The TestLogic-Reset JTAG state can also be used to cancel the programming mode of the ISPPAC-POWR1014/A. UES_READ - This instruction both reads the E2CMOS bits into the UES register and places the UES register between the TDI and TDO pins (as shown in Figure 29), to support programming or reading of the user electronic signature bits. Figure 33. UES Register TDO Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UES_PROGRAM - This instruction will program the content of the UES Register into the UES E2CMOS memory. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. ERASE_DONE_BIT - This instruction clears the 'Done' bit, which prevents the ISPPAC-POWR1014/A sequence from starting. 39 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet PROGRAM_DONE_BIT - This instruction sets the 'Done' bit, which enables the ISPPAC-POWR1014/A sequence to start. RESET - This instruction resets the PLD sequence and output macrocells. IN1_RESET_JTAG_BIT - This instruction clears the JTAG Register logic input 'IN1.' The PLD input has to be configured to take input from the JTAG Register in order for this command to have effect on the sequence. IN1_SET_JTAG_BIT - This instruction sets the JTAG Register logic input 'IN1.' The PLD input has to be configured to take input from the JTAG Register in order for this command to have effect on the sequence. PLD_VERIFY_INCR - This instruction reads out the PLD data register for the current address and increments the address register for the next read. Notes: In all of the descriptions above, OUTPUTS_HIGHZ refers both to the instruction and the state of the digital output pins, in which the open-drains are tri-stated and the FET drivers are pulled low. Before any of the above programming instructions are executed, the respective E2CMOS bits need to be erased using the corresponding erase instruction. 40 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Package Diagrams 48-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0.20 C A-B D D N 0.20 H A-B D D1 3. A 1 E B e D 8. 4X 3. E1 3. SEE DETAIL "A" H b C SEATING PLANE A A2 B GAUGE PLANE 0.25 0.08 M C A -B D 0.08 C LEAD FINISH b 1.00 REF. A1 0.20 MIN. B 0-7 L c c1 b DETAIL "A" 1 BASE METAL SECTION B - B SYMBOL MIN. 0.05 1.35 NOM. 1.40 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.45 0.60 48 0.50 BSC 0.17 0.17 0.09 0.09 0.22 0.20 0.15 0.13 0.27 0.23 0.20 0.16 0.75 MAX. 1.60 0.15 1.45 NOTES: 1. 2. 3. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1 DIMENSIONS. A A1 A2 D D1 E E1 L N e b b1 c c1 5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. 6. SECTION B-B: THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 7. 8. 41 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Part Number Description ISPPAC-POWR1014X - 01XX48X Device Family Device Number ADC Support A = ADC present Operating Temperature Range I = Industrial (-40oC to +85oC) Package T = 48-pin TQFP TN = Lead-Free 48-pin TQFP* Performance Grade 01 = Standard ISPPAC-POWR1014/A Ordering Information Conventional Packaging Part Number ISPPAC-POWR1014A-01T48I ISPPAC-POWR1014-01T48I Package TQFP TQFP Pins 48 48 Lead-Free Packaging Part Number ISPPAC-POWR1014A-01TN48I ISPPAC-POWR1014-01TN48I Package Lead-Free TQFP Lead-Free TQFP Pins 48 48 42 Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Package Options VMON10 RESETB PLDCLK VCCINP VCCD MCLK SDA SCL IN4 IN3 IN2 IN1 48 47 46 45 44 43 42 41 40 39 38 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 30 29 28 27 26 25 VMON9 VMON8 VMON7 VMON6 VMON5 GNDD GNDA VCCA VMON4 VMON3 VMON2 VMON1 ISPPAC-POWR1014A 48-Pin TQFP HVOUT2 HVOUT1 TDISEL TMS TDI TDO SMBA_OUT3 43 VCCPROG ATDI VCCJ TCK VCCD Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Package Options (Cont.) VMON10 RESETB PLDCLK VCCINP GNDD GNDD VCCD MCLK IN4 IN3 IN2 IN1 48 47 46 45 44 43 42 41 40 39 38 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 30 29 28 27 26 25 VMON9 VMON8 VMON7 VMON6 VMON5 GNDD GNDA VCCA VMON4 VMON3 VMON2 VMON1 ISPPAC-POWR1014 48-Pin TQFP HVOUT2 HVOUT1 TDISEL TMS TDI SMBA_OUT3 ATDI TDO Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www.latticesemi.com 44 VCCPROG VCCJ TCK VCCD Lattice Semiconductor ISPPAC-POWR1014/A Data Sheet Revision History Date February 2006 March 2006 Version 01.0 01.1 Initial release. Change Summary ISPPAC-POWR1014/A block diagram: "SELTDI" changed to "TDISEL". Pin Descriptions table: "InxP" changed to "Inx", "MONx" to "VMONx", VMON upper range from "5.75V" to "5.87V". Pin Descriptions table, note 4 - clarification for un-used VMON pins to be tied to GNDD. Absolute Maximum Ratings table and Recommended Operating Conditions table: "VMON+" changed to VMON". Digital Specifications table: add note # 2 to ISINKTOTAL: "Sum of maximum current sink by all digital outputs. Reliable operation is not guaranteed if this value is exceeded." Typographical corrections: Vmon trip points and thresholds Typographical corrections: "InxP" to "Inx", "MONx" to "VMONx". May 2006 01.2 Update HVOUT I source range: 12.5A to 100A Clarify operation of ADC conversions Digital Specifications table, added footnotes on I2C frequency TAP Instructions table, clarify DISCHARGE instruction of JTAG. Added instruction descriptions for others. October 2006 01.3 Data sheet status changed to "Final" Analog Specifications table, reduced Max. ICC to 20 mA. Tightened Input Resistor Variation to 15%. AC/Transient Characteristics table, tightened Internal Oscillator frequency variation down to 5%. Digital Specifications table, included VIL and VIH specifications for I2C interface. March 2007 01.4 Corrected VCCINP Voltage range from "2.25V to 3.6V" to "2.25V to 5.5V". Removed reference to Internal Pull-up resistor for signal line TDO. Corrected the Maximum Vmon Range value from 5.734V to 5.867V. Removed references to VPS[0:1]. August 2007 01.5 Changes to HVOUT pin specifications. 45 |
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